In general, static logic level circuits are circuits that provide one or more constant logic outputs, including static logic one and static logic zero. These constant logic outputs are also known as static logic level outputs. Static logic level outputs are typically used in ICs as tie-offs for input terminals of logic gates not driven by any other driving device or driving signal, except the static logic level outputs. Note that some IC designers refer to these input terminals as “unused” input terminals. Furthermore, in some IC designs, gates that are specified to be coupled to a logic one or a logic zero may be coupled to the corresponding static logic level output.
In general, an indirect connection (also known as a “soft” connection) to a static logic one or a static logic zero is preferred because a direct connection of a gate to a power supply or ground may cause Electro-Static Discharge (ESD) failures in the IC. This is especially serious with some advanced technologies because the devices may have relatively thin gate oxide, and hence, are more susceptible to ESD.
Four conventional circuits for providing a static logic one or a static logic zero are shown in FIGS. 1A and 1B and in FIGS. 2A and 2B. The circuit 101 shown in FIG. 1A uses a diode-connected transistor 110 to provide an intermediate voltage to drive the gate of the n-type Metal Oxide Semiconductor (NMOS) transistor 120, which in turn generates a static logic zero. Likewise, the circuit 102 shown in FIG. 1B uses a diode-connected transistor 112 to provide an intermediate voltage to drive the gate of the p-type Metal Oxide Semiconductor (PMOS) transistor 122, which in turn generates a static logic one.
The circuits 201 and 202 shown in FIGS. 2A and 2B are similar to those in FIGS. 1A and 1B. However, instead of using a diode-connected transistor, each of the circuits 201 and 202 uses a resistor instead. Referring to FIG. 2A, one end of the resistor 210 is coupled to a power supply and the other end is coupled to the gate of the NMOS transistor 220 to drive the NMOS transistor 220. Likewise, one end of the resistor 212 in FIG. 2B is grounded and the other end is coupled to the gate of the pMOS transistor 222 to drive the pMOS transistor 222. As a result, the intermediate nodes, Int, in both circuits 201 and 202 are driven to a full power supply or rail value.
One disadvantage of the conventional circuits 101 and 102 is that the intermediate nodes, Int, may not be at the full rail logic level, and hence, the voltages at the intermediate nodes may not drive the transistors 120 and 122 as strongly as if the intermediate nodes were at the full rail logic level. Consequently, the transistors 120 and 122 may be at the edge of “cutoff.”
Another disadvantage of the conventional circuits 101 and 102 is their susceptibility to crosstalk. Crosstalk generally refers to noise events that may cause the static logic level output to switch to an undesired logic state for some period of time during the noise events. The circuits 101 and 102 rely on a high impedance node that is not at the full power supply rail voltage (e.g., the intermediate node, Int) to drive the gate of a transistor. This is problematic when the transistor threshold voltage (Vt) becomes large relative to the power supply. If the Vt of the transistors 120 and 122 is too large relative to the power supply, then the voltage at the intermediate node, Int, may not be strong enough to activate the transistors 120 and 122 sufficiently to achieve a good drive strength in the static logic level outputs. This condition, along with the high-impedance nature of the intermediate node, leads to crosstalk susceptibility.
A disadvantage of the second type of conventional circuits 201 and 202 in FIGS. 2A and 2B is that the resistors 210 and 212 typically occupy a large amount of area on a die in order to effectively prevent ESD failures, and thus, resulting in a large area penalty. Moreover, since the required resistance of the resistors 210 and 212 is usually large (e.g., about 1 Kohms or higher), the intermediate node, Int, in FIGS. 2A and 2B will be in a relatively high impedance state. Thus, the noise issues associated with crosstalk discussed above may apply to the circuits 201 and 202 as well.